Fabless Design of Photonic Integrated Circuits within the AIM Foundry Ecosystem

 

Instructors:

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• Prof. Stefan Preble (Rochester Institute of Technology)

• Prof. Jaime Cardenas (University of Rochester)

• Prof. Alan Kost (University of Arizona)

• Prof. Greg Howland (Rochester Institute of Technology)

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This eight-week online edX course, which includes a two-week break in the middle to focus on designing, introduces students and industry professionals to the fabless design of silicon Photonic Integrated Circuits (PICs), using industry-leading Electronic Photonic Design Automation (EPDA) software tools. Registrants are guided through a step-by-step design sequence that culminates in the tape-out of an electro-optically active PIC chip that is suitable for fabrication by AIM Photonics Institute’s Multi-Project-Wafer (MPW) facility. 

 

You can audit the course for free.  Paid registration ($559) includes access to the AIM Photonics Virtual Design Center, with industry-leading Electronic Photonics Design Automation (EPDA) tools.  The registration fee (select "Upgrade to Verified" when registering) also allows you to earn a Verified Certificate of Achievement. 

 

The course is structured around the design of a basic “transceiver” (fiber-coupler+modulator+detector). It begins with an overview of fabless PIC design and a review of passive Silicon Photonic devices  (waveguides, bends, splitters/combiners and interferometers). Registrants are then walked through the process of designing the transceiver chip with a focus on the two primary active devices (electro-optic modulator and photodetector). The course emphasizes the creation of compact models of the devices in order to facilitate the flexible simulation and layout of arbitrary PIC chip designs.  Specifically, registrants will acquire an accomplished mastery of EPDA software tools, using AIM’s Academic Process Design Kit library, and learn how to interpret design guides, leverage hierarchical design, and ensure that the design can be made by the foundry by using Design Rule Checking (DRC).

 

The course is completed and credit earned with each registrant submitting a tape-out of their PIC design.  This course is the first offering in a planned sequence of edX courses instructing in PDK and EPDA-based PIC design; application-specific PIC design; and dense electronic-photonic integration PIC design.

 

There will be no cap on the number of people who can register for the course.  We anticipate that the course commitment will be 15-20 hours a week for eight weeks, including a two-week break in the middle to focus on designing.

 

Optional, non-credit workshop: After completion of the course, select submitted PIC tape-outs may be eligible for free submission to an AIM Photonics MPW run. This limited batch of fabricated PICs will be characterized in a subsequent testing workshop at the Rochester Institute of Technology and AIM’s Test, Assembly and Packaging (TAP) facility, where attendees will learn how to test and analyze the performance of the PICs.